1. Field of the Invention
This invention generally relates to electronic circuitry and, more particularly, to a one-gate delay latch with a shadow stage, which is immune from corruption, to support the latch in its opaque (hold) phase.
2. Description of the Related Art
Whether it is a phase-based design implemented with latches as a fundamental memory element, or edge-based design implemented with back-to-back latches (flip-flops) as the fundamental memory element, latches are an essential building block in modern very large scale integration (VLSI) designs. With conflicting properties of delay, area, power, and robustness, it is difficult to design latches that satisfy all design requirements.
Latches are commonly used in VLSI designs either by themselves or as part of an edge-triggered Flip-Flop (FF) due to their memory holding function. A latch has two phases of operation: in the transparent phase, data flows freely from D to Q, and the amount of time for this to occur is its native delay (Tdq). In the opaque phase, data may toggle on the input D, but Q holds its previous value. Which phase the latch operates in is determined by the phase of the clock input. In the context of being a FF building block, there are setup time (Tsu) and clock delay (Tcq) characteristics of the FF. However, those two parameters together form the Tdq native delay, and it is useful to discuss this value as the metric for performance.
FIGS. 1A and 1B are schematic diagrams of a pass gate (prior art). As configured, when the clock signal (CLK) is low, the device is in a tri-state mode, meaning the output impedance is high. When CLK is high, the input signal (D) is passed to the output. Alternatively, the CLK signal can be connected to the gate of the PMOS transistor and the inverted CLK signal (CK1) connected to the gate of the NMOS transistor, in which case the input is passed when CLK is low. The device of FIG. 1A may also be depicted as shown in FIG. 1B.
FIG. 2 is a schematic diagram of a conventional latch design using pass gates (prior art). The latch is a clocked state element (from D to D1), which is protected from the output by an inverter (from D1 to Q). This design has the benefit of being simple to understand and extremely robust. However, it has two gate-delay elements, which limits its performance. Note: CLK and CK1 are opposite phases of a binary clock signal.
FIG. 3 is a schematic diagram of a conventional latch design with improved gate delay (prior art). As an alternative to the design of FIG. 2, the output inverter is removed to provide a faster Tdq. However, this design has a major flaw in that the memory state element is exposed to the output. The memory state is the output value maintained by pass gate 302, when pass gate 300 is in its opaque phase. When the memory state is protected by the inverter, as in FIG. 2, the effects of any external coupling effects are minimized. When the memory state is exposed, as in FIG. 3, uncontrolled external routes and coupling events can directly affect the feedback loop's ability to maintain the state. If this happens, the memory state becomes corrupted and irrecoverable.
FIG. 4 is a timing diagram contrasting the differences in delay between the circuits of FIG. 2 and FIG. 3. In terms of gate delay, the right-most figure, associated with the latch of FIG. 3, is one gate faster than the left-most figure, which is associated with the latch of FIG. 2.
FIG. 5 is a timing diagram depicting the differences in memory state corruption between the circuits of FIG. 2 and FIG. 3. The diagram illustrates a glitch event from external routing upon the output pin Q. If the state-node is exposed as in FIG. 3, an external aggressor net “Agg” can potentially flip the state of the latch (left-most figure). In the design of FIG. 2, a noise event can only produce a glitch on Q instead of flipping the state of the latch (right-most figure).
FIG. 6 is a schematic drawing of a conventional edge-triggered flip-flop using pass gates (prior art). Edge-triggered flip-flops are commonly used in high-performance synchronous designs due to their robustness and ease of use. A FF is made up of two latches, conventionally described as master and slave latches. As shown, each latch is based upon the design depicted in FIG. 2. Each of these latches is transparent in alternating clock phases, and this creates the functionality of a FF. The delay characteristics of a FF are described by its delay through the master latch (Tsu), the delay through the slave latch (Tcq) and hold time (Thd). Of the three characteristics, Tsu and Tcq are sometimes combined as the total FF delay (Tdq) to describe the overall delay characteristic of the FF.
The key elements of the flip-flop are its master latch state nodes (MS) and its slave latch state nodes (SS). The state nodes of latches are made up of clocked cross-coupled pass gates to provide a feedback loop. This feedback loop maintains the state of this memory element when the latch is opaque. Therefore, these state nodes must be carefully designed to prevent any noise related glitch event from corrupting the state of the latch.
It would be advantageous if a latch could be designed to combine the improved gate delay of the FIG. 3 circuit, with the noise immunity of the FIG. 2 circuit.